# Analysis of Clamping Circuit

The clamping network is one that clamps a signal to a different DC level. The network contains a capacitor, a diode, and a resistive element, but it can also have an independent DC supply source to introduce an additional shift in voltage level. The magnitude of R and C to be used in the Clamper Circuit must be chosen such that the time constant Ƭ = RC is large enough to ensure that the voltage across the capacitor does not discharge significantly during the interval the diode is non-conducting. In our discussion, we will assume that for all practical purposes the capacitor will fully charge or discharge in five time constants.

The network shown in figure below will clamp the input signal to the zero level for ideal diodes. The resistor R is the load resistor or a parallel combination of the load resistor and a resistor designed to provide the desired level of R as determined by Ƭ = RC.

The above circuit can be can be well understood in two cases.

**Case1: When 0< t < T/2, Diode Forward Biased**

For the above time period, the diode will conduct and the circuit can be represented as shown below.

As clear from the above circuit, the diode shorts the Resistor R and hence the time constant Ƭ = RC is very small determined by the lead resistance. Therefore the Capacitor C gets quickly charged. As the output voltage is appearing across the short circuit, therefore Vo = 0.

**Thus for 0 < t < T/2,**

**V _{o} = 0**

**Case2: When T/2 < t < T, Voltage changes to -V and Diode Reversed Biased**

For this time period the diode does not conduct and acts like an open circuit. For this time period, the clamper circuit can be simply represented as shown below.

In this time period, the Capacitor will start discharging and as time constant of RC network is chosen high enough, the capacitor will not discharge completely till five time constant but before completely discharging the capacitor input voltage will again change its state from –V to + V assuming T < Ƭ.

Therefore during the above period,

V_{o} = -V –V = -2V

**Thus for T / 2 < t < T,**

**V _{o} = -2V**

Combining the two cases, we can get the waveform for Clamper Circuit as shown below.

From the above waveform we see that, total swing of the output is equal to the total swing of the input signal in a Clamper Circuit.

**Some helpful tips for analyzing Clamper Circuit:**

1) Start the analysis of clamping networks by considering that part of the input signal that will forward bias the diode.

2) During the period that the diode is in the forward biased state, assume that the capacitor will charge up instantaneously to a voltage level determined by the network.

3) Assume that during the period when the diode is in the reversed biased state the capacitor will hold on to its established voltage level.

4) Throughout the analysis maintain a continual awareness of the location and reference polarity for V_{o} to ensure that the proper levels for V_{o} are obtained.

5) Keep in mind the general rule that the total swing of the total output must match the swing of the input signal.